The present invention relates to a pulse latch circuit and a power saving technique for use therein and relates to a technique that is effectively applicable to a semiconductor integrated circuit such as, for example, a microcomputer.
Component circuits that are important for performance enhancement and power saving of a semiconductor integrated circuit are memory elements typified by flip-flop (hereinafter abbreviated to “FF”) circuits or latch circuits. Here, a “FF circuit” means a memory element that captures an input signal on the rising edge of a clock and a “latch circuit” means a so-called level-sensing type circuit that transfers an input signal to an output terminal during an “H” (high level) period of a clock and retains an output signal during an “L” (low level) period of a clock. A variety of circuits and clock systems have been proposed with the aim of the speed-up and power saving of the FF circuits or latch circuits. As the size of semiconductor integrated circuits becomes larger, adaptation for a technique of a design (design for test, DFT) providing an easy way of testing FF circuits is becoming necessary from a perspective of the testing cost.
A technique intended for speed-up by replacing the FF circuits by pulse latch circuits is known. For example, according to a technique described in Patent Document 1, in a semiconductor integrated circuit including a clock pulse generating circuit which generates a pulsed clock signal, a predetermined combinational logic circuit, a pulse latch circuit that can latch input data to the pulsed clock signal, located before or after the combinational logic circuit, the influence of uncertainty of the clock edges is eliminated by setting the pulse width of the pulsed clock signal to fulfill a certain condition.
[Patent Document 1] A brochure of Internal Publication No. WO 2004/038917A1